3d7444 monolithic quad 4-bit programmable delay line (series 3d7444) features ? four indep?t programmable lines on a single chip ? all-silicon cmos technology ? low quiescent current (1ma typical) ? leading- and trailing-edge accuracy ? vapor phase, ir and wave solderable ? auto-insertable (dip pkg.) ? increment range: 1.5ns through 25ns ? delay tolerance: 1ns or 2% (see table 1) ? temperature stability : 2% typical (0c-70c) ? vdd stability : 1% typical ? minimum input pulse w i dth: 10% of total delay functional description the 3d7444 device is a small, versatile, quad 4-bit programmable monolithic delay line. delay values, pr ogrammed via the serial interface, can be independently varied over 15 equal steps. the step size (in ns) is determined by the device dash number. each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. for each line, the delay time is given by: td n = t0 + a n * ti where t0 is the inherent delay, a n is the delay address of the n-th line and ti is the delay increment (dash number). the desired addresses are shifted into the device via the sc and si inputs, and the addresses are latched using the al input. the serial interface can also be used to enable/disable each delay line. the 3d7444 operates at 5 volts and has a typical t0 of 6ns. the 3d7444 is cmos-compatible, capable of sourcing or sinking 4ma loads, and features both rising- and falling-edge accuracy. the device is offered in a standard 14-pin auto-insertable dip and a space saving surface mount 14-pin soic. packages 14 13 12 11 10 9 8 1 2 3 4 5 6 7 i1 sc i2 i3 i4 si gnd vdd a l o1 so o2 o3 o4 dip - 14 3 d 74 44 -x x 1 2 3 4 5 6 7 14 13 12 11 10 9 8 i1 sc i2 i3 i4 si gn d vd d a l o1 so o2 o3 o4 so i c - 1 4 3d 7444d- x x pin descriptions i1-i4 signal inputs o1-o4 signal outputs al address latch in sc serial cloc k in si serial data in so serial data out vdd 5.0v gnd ground table 1: part number specifications dela ys a nd tolera nces (ns) input restrictions delay total inherent max freq. (mhz ) min p.w . (ns) pa rt number i n c r e m e n t delay delay r e c o m m e n d e d a b s o l u t e r e c o m m e n d e d a b s o l u t e 3d7444-1.5 1.5 1.00 22.5 1.0 6 2.0 2 0 . 0 1 6 6 2 5 . 0 3 . 0 3d7444-2 2.0 1.50 30.0 1.0 6 2.0 1 3 . 8 1 6 6 3 6 . 0 3 . 0 3d7444-4 4.0 2.00 60.0 1.2 6 2.0 7 . 5 7 8 3 . 3 6 6 . 0 6 . 0 3d7444-5 5.0 2.25 75.0 1.5 6 2.0 6 . 1 7 6 6 . 6 8 1 . 0 7 . 5 3d7444-8 8.0 3.00 120 2.4 6 2.0 3 . 9 6 4 1 . 6 1 2 6 . 0 1 2 . 0 3d7444-10 10 3.00 150 3.0 6 2.0 3 . 2 0 3 3 . 3 1 5 6 . 0 1 5 . 0 3d7444-15 15 4.00 225 4.5 6 2.0 2 . 1 6 2 2 . 2 2 3 1 . 0 2 2 . 5 3D7444-20 20 6.00 300 6.0 6 2.0 1 . 6 3 1 6 . 6 3 0 6 . 0 3 0 . 0 3d7444-25 25 7.00 375 7.5 6 2.0 1 . 3 1 1 3 . 3 3 8 1 . 0 3 7 . 5 notes: a n y increment betw een 1.5 and 25 ns not show n is also av ailable as standard total delay is giv e n by delay at address 15 minus delay at address 0 ? 2003 data delay dev i ces f o r mechanical dimensions, click here . f o r package marking details, click here . doc #03006 data delay devices, inc. 1 12/8/03 3 mt. prospect ave. clifton, nj 07013
3d7444 application notes line to its normal operation. the device contains an so output, which can be used to cascade multiple devices, as shown in figure 3. theory of operation the quad 4-bit programmable 3d7444 delay line architecture is comprised of a number of delay cells connected in series with their respective outputs multiplexed onto the delay out pin (o1- o4) by the user-selected programming data. each delay cell produces at its output a replica of the signal present at its input, shifted in time. each of the four lines can be controlled independently, via the serial interface. table 2: bit sequence b i t d e l a y line function 1 4 output e n a b l e 2 3 output e n a b l e 3 2 output e n a b l e 4 1 output e n a b l e 5 address bit 3 6 address bit 2 7 address bit 1 8 1 address bit 0 9 address bit 3 10 address bit 2 11 address bit 1 12 2 address bit 0 13 address bit 3 14 address bit 2 15 address bit 1 16 3 address bit 0 17 address bit 3 18 address bit 2 19 address bit 1 20 4 address bit 0 programmed delay (address) interface figure 1 illustrates the main functional blocks of the 3d7444 device. since the device is a cmos design, all unused input pins must be returned to well defined logic levels (vdd or gnd). the delays are adjusted by first shifting a 20-bit programming word into the device via the sc and si pins, then strobing the al signal to latch the values. the bit sequence is shown in table 2 , and the associated timing diagram is shown in figure 2 . each line has associated with it an enable bit. setting this bit low will force the corresponding delay line output to a high impedance state, while setting it high returns the delay line 20 - b it l a t c h 2 0 - b i t s h i f t reg i st er so f i g u r e 1: f u n c t i o n al b l o ck d i ag r a m delay line delay li n e delay li n e i4 i3 i2 i1 o4 o3 o2 o1 a l si sc enabl es addr 4 a ddr 3 a ddr 2 a d dr1 doc #03006 data delay devices, inc. 2 12/8/03 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7444 power supply and temperature considerations programmed delay (address) update the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3d7444 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. a delay line is a memory device. it stores information present at the input for a time equal to the delay setting before presenting it at the output with minimal distortion. each 4-bit delay line in the 3d7444 can be represented by 15 serially connected delay elements (individually addressed by the programming data), each capable of storing data for a time equal to the device increment (step time). the delay line memory property, in conjunction with the operational requirement of ?instantaneously? connecting the delay element addressed by the programming data to the output, may inject spurious information ont o the output data stream. the thermal coefficient is reduced to 400 ppm/c , which is equivalent to a variation, over the 0c-70 c operating range, of 2% from the room-temperature delay settings. the pow er supply coefficient is reduced, over the 4.75v- 5.25v operating range, to 1.5% of the delay settings at the nominal 5vdc power supply and/or 2ns , whichever is greater. in order to ensure that spurious outputs do not occur, it is essential that the input signal be idle (held high or low) for a short duration prior to updating the programmed delay. this duration is given by the maximum programmable delay. satisfying this requirement allows the delay line to ?clear? itself of spurious edges. when the new address is loaded, the input signal can begin to switch (and the new delay will be valid) after a time given by t pdv or t edv (see section below). it is essential that the pow er supply pin be adequately by passed and filtered. in addition, the pow er bus should be of as low an impedance construction as possible. pow e r planes are preferred. ne w val u e s ne w bi t 1 ne w bi t 2 0 ne w bi t 2 ol d bi t 1 ol d bi t 2 ol d bi t 2 0 la t c h (al ) cl ock (sc) ser ial in pu t ( si ) ser ial out p ut ( so ) de l a y ti m e s t lw t cw t cw t cs l t ds c t dh c t pc q t ld v t ld x pr evio u s val u e s f i g u r e 2: s e ri al i n t e rf ace t i mi n g d i ag ram ne w bi t 1 from w r it ing device to nex t device si so sc a l 3d7444 3d7444 3d7444 f i g u r e 3: cascad in g m u lt ip le dev i ces si so sc a l si so sc a l doc #03006 data delay devices, inc. 3 12/8/03 3 mt. prospect ave. clifton, nj 07013
3d7444 doc #03006 data delay devices, inc. 4 12/8/03 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com input signal considerations the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay and increment accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore a recommended and an absolute maximum operating input frequency and a recommended and an absolute minimum operating pulse width have been specified. operating frequency the absolute maximum operating frequency specification, tabulated in table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. the recommended maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. operation above the recommended maximum frequency will cause the delays to shift slighty with respect to their values at low-frequency operation. the magnitudes of these deviations will increase as the absolute maximum frequency is approached. however, if the input frequency and pulse width remain constant, the device will exhibit the same delays from one period to the next (ie, no appreciable jitter). operating pulse width the absolute minimum operating pulse width (high or low) specification, tabulated in table 1, determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. the minimum operating pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in table 1 is guaranteed. operation below the recommended minimum pulse width will cause the delays to shift slighty with respect to their values at long-pulse-width operation. the magnitudes of these deviations will increase as the absolute minimum pulse width is approached. however, if the input pulse width and frequency remain constant, the device will exhibit the same delays from one period to the next (ie, no appreciable jitter).
3d7444 doc #03006 data delay devices, inc. 5 12/8/03 3 mt. prospect ave. clifton, nj 07013 device specifications table 3: absolute maximum ratings parameter symbol min max units notes dc supply voltage v dd -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v input pin current i in -10 10 ma 25c storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 4: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min typ max units notes static supply current* i dd 1.3 2.0 ma v dd = 5.25v high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih -0.1 0.0 0.1 p a v ih = v dd low level input current i il -0.1 0.0 0.1 p a v il = 0v high level output current i oh -8.0 -6.0 ma v dd = 4.75v v oh = 2.4v low level output current i ol 6.0 7.5 ma v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 ns c ld = 5 pf *i dd (dynamic) = 4 * c ld * v dd * f input capacitance = 10 pf typical where: c ld = average capacitance load/line (pf) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz) table 5: ac electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min typ max units notes latch width t lw 10 ns data setup to clock t dsc 10 ns data hold from clock t dhc 1 ns clock width (high or low) t cw 15 ns clock setup to latch t csl 20 ns clock to serial output t pcq 12 20 ns latch to delay valid t ldv 35 45 ns 1 latch to delay invalid t ldx 5 ns 1 input pulse width t wi 10 % of total delay see table 1 input period period 20 % of total delay see table 1 input to output delay t plh , t phl ns see text notes: 1 - refer to programmed delay (address) update section
3d7444 silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vdd): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.3v 0.1v threshold: 1.65v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.7v ) pulse width: pw in = 1.25 x total delay period: per in = 2.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out1 out2 out4 out3 out tr i g in ref tr i g fi gu r e 4 : t e st s e tu p dev i ce un de r t e st ( dut ) di g i t a l sco p e/ t i m e i n t e rva l co unt er pu l s e ge ne ra t o r in 4 co m p ut er sy st em pr i n t e r in 3 in 2 in 1 figur e 5 : t i m i ng d i a g r a m t pl h t ph l per in pw in t ris e t fa l l 0. 6v 0. 6v 1. 65v 1. 65v 2. 7v 2. 7v 1. 65v 1. 65v v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #03006 data delay devices, inc. 6 12/8/03 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
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